MECHATROLINK-Ⅲ Master / Slave IP core

Built-in parts (ASIC etc)

Master function or Slave function__RCMS_CONTENT_BOUNDARY__Built-in CPU in FPGA enables to perform intelligent function using RTOS with one chip__RCMS_CONTENT_BOUNDARY__Synchronized to a clock of up to 66 MHz, connectable to a high-speed synchronous bus such as PCI without reduced throughput__RCMS_CONTENT_BOUNDARY____RCMS_CONTENT_BOUNDARY____RCMS_CONTENT_BOUNDARY____RCMS_CONTENT_BOUNDARY____RCMS_CONTENT_BOUNDARY____RCMS_CONTENT_BOUNDARY____RCMS_CONTENT_BOUNDARY__

Item Specifications Target FPGA Xilinx Spartan®-6 LX FPGA / Spartan-6 LXT FPGA / Zynq®-7000 SoC Network Interface MECHATROLINK-Ⅲ Network ×2 port (MⅡ I/F 100Mbps Full Duplex designated) Host Interface 32bit shared memory interface / 32bit register interface Host Interrupt 2 level Interrupt request output Host Interface Byte Order Little endian Product Type TIP-ML3MST-S6/7Z-PROJ (MECHATROLINK-Ⅲ Master Dedicated IP) TIP-ML3SLV-S6/7Z-PROJ (MECHATROLINK-Ⅲ Slave Dedicated IP)